SOI technology consists in separating a thin silicon layer (a few nanometers in thickness) on a silicon substrate by a relatively thick (a few tens of nanometers in thickness, as a general rule) insulating layer.
Integrated circuits produced in SOI technology have a certain advantages. Such circuits generally have lower power consumption for an equivalent performance. Such circuits also have lower parasitic capacitances, thereby allowing switching speeds to be improved.
In addition, the phenomenon of latch up encountered in bulk technology MOS transistors may be prevented. Such circuits therefore prove to be particularly suitable for SoC or MEMS applications.
It has also been observed that SOI integrated circuits are less sensitive to the effects of ionizing radiation and thus prove to be more reliable in applications where such radiation may cause malfunctions, especially in space applications.
SOI integrated circuits may notably comprise active SRAM memory or logic gates.
Many studies have focused on reducing the static consumption of logic gates while increasing their switching speed. Certain integrated circuits currently being developed incorporate both low-consumption logic gates and fast-access logic gates. To generate these two types of logic gates in a given integrated circuit, the threshold voltage of certain transistors of the fast-access logic gates is reduced and the threshold voltage of other transistors of the low-consumption logic gates is increased.
In bulk technology, modulation of the threshold voltage level of transistors of the same type is achieved by modifying the doping level in their channels. However, in fully depleted silicon-on-insulator technology (“FDSOI”), the doping of the channel is almost non-existent (1015 cm−3). Thus, the doping level of the channel of the transistors cannot be made to vary substantially. This prevents the threshold voltages from being modified in the conventional way.
A known way to produce transistors of the same type with different threshold voltages is to use different gate materials in these transistors. However, in practice producing such an integrated circuit proves to be technically difficult and economically prohibitive.
Another known way to use FDSOI technology to produce different transistors with different threshold voltages is to place an electrically biased ground plane between a thin insulating oxide layer and the silicon substrate. By adjusting the doping of the ground planes and their biases, it is possible to define a range of threshold voltages for these various transistors. It is thus possible to produce transistors with a low threshold voltage (typically 400 mV), termed “LVT” (for “Low Voltage Threshold”) transistors, transistors with a high threshold voltage (typically 550 mV), termed “HVT” (for “High Voltage Threshold”) transistors, and transistors with an intermediate threshold voltage (typically 450 mV), termed “SVT” (for “Standard Voltage Threshold”) transistors.
For these various transistors to function, it is necessary to isolate them electrically from each other. Therefore, the transistors are generally encircled by trench isolations (denoted by the acronym “STI” for “Shallow Trench Isolation”) that extend as far as their wells.
Such integrated circuits also include devices to protect them from accidental electrostatic discharges (“ESD”) that may deteriorate these transistors. A particularly useful ESD protection device is semiconductor-controlled rectifier (SCR). An SCT is able to handle a high discharge current density. In addition, its turn-on trigger can be finely tuned.
However, SCRs have drawbacks. Specifically, SCRs have a relatively slow switching speed before discharge current is conducted. This results in a relatively large transient overvoltage amplitude. Additionally, SCTs are sensitive to parasitic turn-on, in particular if currents are injected near the device.